ATAR862-4_06 Datasheet, PDF (7/112 Pages) ATMEL Corporation – Microcontroller with UHF ASK/FSK Transmitter

ATAR862-4
Figure 7-1.
Tolerances of Frequency Modulation
~
V_S
XTAL
C_Stray1
C_M L_M
R_S
C₀
Crystal equivalent circuit
C_Stray2
C₄
C₅
C_Switch
Using C₄ = 9.2 pF ±2%, C₅ = 6.8 pF ±5%, a switch port with CS_witch = 3 pF ±10%, stray capaci-
tances on each side of the crystal of C_Stray1 = C_Stray2 = 1 pF ±10%, a parallel capacitance of the
crystal of C₀ = 3.2 pF ±10% and a crystal with C_M = 13 fF ±10%, an FSK deviation of ±21 kHz
typical with worst case tolerances of ±16.3 kHz to ±28.8 kHz results.
7.3 CLK Output
An output CLK signal is provided for a connected microcontroller. The delivered signal is CMOS
compatible if the load capacitance is lower than 10 pF.
7.3.1
Clock Pulse Take Over
The clock of the crystal oscillator can be used for clocking the microcontroller. The microcontrol-
ler block has the special feature of starting with an integrated RC-oscillator to switch on the PLL
transmitter block with ENABLE = H, and after 1 ms to assume the clock signal of the transmis-
sion IC, so the message can be sent with crystal accuracy.
7.3.2
Output Matching and Power Setting
The output power is set by the load impedance of the antenna. The maximum output power is
achieved with a load impedance of Z_Load,opt = (166 + j223) Ω. There must be a low resistive path
to V_S to deliver the DC current.
The delivered current pulse of the power amplifier is 9 mA and the maximum output power is
delivered to a resistive load of 465 Ω if the 1.0 pF output capacitance of the power amplifier is
compensated by the load impedance.
An optimum load impedance of:
Z_Load = 465 Ω || j/(2 × π 1.0 pF) = (166 + j223) Ω thus results for the maximum output power of
7.5 dBm.
The load impedance is defined as the impedance seen from the PLL transmitter block’s ANT1,
ANT2 into the matching network. Do not confuse this large signal load impedance with a small
signal input impedance delivered as input characteristic of RF amplifiers and measured from the
application into the IC instead of from the IC into the application for a power amplifier.
Less output power is achieved by lowering the real parallel part of 465 Ω where the parallel
imaginary part should be kept constant.
Output power measurement can be done with the circuit shown in Figure 7-2 on page 8. Note
that the component values must be changed to compensate the individual board parasitics until
the PLL transmitter block has the right load impedance Z_Load,opt = (166 + j223) Ω. Also the damp-
ing of the cable used to measure the output power must be calibrated.
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4552G–4BMCU–09/06