ATAR862-4_06 Datasheet, PDF (56/112 Pages) ATMEL Corporation – Microcontroller with UHF ASK/FSK Transmitter

Table 22-10. Timer 2 Output Select Bits
Output
Mode T2OS2 T2OS1 T2OS0 Clock Output
1
1
1
1
Toggle mode: a Timer 2 compare match toggles the output
flip-flop (M2) -> T2O
2
1
1
0
Duty cycle burst generator 1: the DCG output signal (DCG0)
is given to the output and gated by the output flip-flop (M2)
Duty cycle burst generator 2: the DCG output signal (DCGO)
3
1
0
1
is given to the output and gated by the SSI internal data
output (SO)
4
1
0
0
Biphase modulator: Timer 2 modulates the SSI internal data
output (SO) to Biphase code
5
0
1
1
Manchester modulator: Timer 2 modulates the SSI internal
data output (SO) to Manchester code
6
0
1
0
SSI output: T2O is used directly as SSI internal data output
(SO)
7
0
0
1
PWM mode: an 8-/12-bit PWM mode
8
0
0
0
Not allowed
If one of these output modes is used the T2O alternate function of Port 4 must also be activated.
22.12.5
Timer 2 Compare and Compare Mode Registers
Timer 2 has two separate compare registers, T2CO1 for the 4-bit stage and T2CO2 for the 8-bit
stage of Timer 2. The timer compares the contents of the compare register current counter value
and if it matches it generates an output signal. Dependent on the timer mode, this signal is used
to generate a timer interrupt, to toggle the output flip-flop as SSI clock or as a clock for the next
counter stage.
In the 12-bit timer mode, T2CO1 contains bits 0 to 3 and T2CO2 bits 4 to 11 of the 12-bit com-
pare value. In all other modes, the two compare registers work independently as a 4- and 8-bit
compare register.
When assigned to the compare register a compare event will be suppressed.
56 ATAR862-4
4552G–4BMCU–09/06