AT80C5112 Datasheet, PDF (7/97 Pages) ATMEL Corporation – 8-bit Microcontroller with A/D Converter

AT8xC5112
Table 2. Pin Description (Continued)
Mnemonic
PIN NUMBER
LQFP PLCC
48
52
TYPE
Name and Function
AIN4 (P4.4): A/D converter input 4
I/O
MISO: Master IN, Slave OUT of the SPI controller
AIN5 (P4.5): A/D converter input 5
I/O
MOSI: Master OUT, Slave IN of the SPI controller
AIN6 (P4.6): A/D converter input 6
I/O
SPSCK: Clock I/O of the SPI controller
I/O AIN7 (P4.7): A/D converter input 7
P0.0-P0.7
X
X
I/O Port 0: Port 0 is an open-drain, bi-directional I/O port. Port 0 pins that have 1s written to them float and can be
used as high impedance inputs. Port 0 is also the multiplexed low-order address and data bus during access to
external program and data memory. In this application, it uses strong internal pull-up when emitting 1s.
P2.0-P2.7
X
X
I/O Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1s written to them
are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally
pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during
fetches from external program memory and during accesses to external data memory that use 16-bit
addresses (MOVX atDPTR). In this application, it uses strong internal pull-ups emitting 1s. During accesses to
external data memory that use 8-bit addresses (MOVX atRi), port 2 emits the contents of the P2 SFR.
RST
X
X
I RST: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal
diffused resistor to V_SS permits a power-on reset using only an external capacitor to V_CC. If the hardware
watchdog reaches its time-out, the reset pin becomes an output during the time the internal reset is activated.
ALE
X
X
O Address Latch Enable: Output pulse for latching the low byte of the address during an access to external
memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency,
and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to
external data memory. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive
during internal fetches.
PSEN
X
X
O Program Store Enable: The read strobe to external program memory. When executing code from the external
program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped
during each access to external data memory. PSEN is not activated during fetches from internal program
memory.
EA
X
X
I External Access Enable: EA must be externally held low to enable the device to fetch code from external
program memory locations 0000H and 1FFFH . If EA is held high, the device executes from internal program
memory unless the program counter contains an address greater than 1FFFH. EA must be held low for
ROMless devices. If security level 1 is programmed, EA will be internally latched on Reset.
XTAL1
X
I XTAL1 : Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
XTAL2
X
O XTAL2 : Output from the inverting oscillator amplifier.
7
4191B–8051–04/03