AT43USB320A_04 Datasheet, PDF (7/115 Pages) ATMEL Corporation – Full-speed USB Microcontroller with an Embedded Hub

Architectural
Overview
1443E–USB–4/04
AT43USB320A
The peripherals and features of the AT43USB320A microcontroller are similar to those of the
AT90S8515, with the exception of the following modifications:
• External Program Memory
• No EEPROM
• No external data memory accesses
• No Analog Comparation
• Idle mode not supported
• USB Hub with attached function
• No internal pull-ups in the general-purpose I/O pin PA, PB, PC, PD
The embedded USB hardware of the AT43USB320A is a compound device, consisting of a 5
port hub with a permanently attached function on one port. The hub and attached function are
two independent USB devices, each having its own device addresses and control endpoints.
The hub has its dedicated interrupt endpoint, while the USB function has 2 additional program-
mable endpoints with separate 8-byte FIFOs.
The microcontroller always runs from a 12 MHz clock that is generated by the USB hardware.
While the nominal and average period of this clock is 83.3 ns, it may have single cycles that
deviate by ±20.8 ns during a phase adjustment by the SIE's clock/data separator of the USB
hardware.
The microcontroller shares most of the control and status registers of the megaAVR^™ Micro-
controller Family. The registers for managing the USB operations are mapped into its SRAM
space. The I/O section on page 16 summarizes the available I/O registers. The “AVR Register
Set” on page 36 covers the AVR registers. Please refer to the Atmel AVR manual for more
information.
The fast-access register file concept contains 32 x 8-bit general-purpose working registers
with a single clock cycle access time. This means that during one single clock cycle, one Arith-
metic Logic Unit (ALU) operation is executed. Two operands are output from the register file,
the operation is executed, and the result is stored back in the register file – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing - enabling efficient address calculations. One of the three address pointers
is also used as the address pointer for look-up tables in program memory. These added func-
tion registers are the 16-bit X-, Y- and Z-registers.
The ALU supports arithmetic and logic operations between registers or between a constant
and a register. Single register operations are also executed in the ALU. Figure 2 on page 6
shows the AT43USB320A AVR Enhanced RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be used
on the register file as well. This is enabled by the fact that the register file is assigned the 32
lowest Data Space addresses ($00 - $1 F), allowing them to be accessed as though they were
ordinary memory locations.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-
ters, Timer/Counters, and other I/O functions. The I/O Memory can be accessed directly, or as
the Data Space locations following those of the register file, $20 - $5F.
The AVR uses a Harvard architecture concept – with separate memories and buses for pro-
gram and data. The program memory is executed with a single-level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory.
This concept enables instructions to be executed in every clock cycle. The program memory is
a downloadable SRAM or a mask programmed ROM.
With the relative jump and call instructions, the whole 24K address space is directly accessed.
Most AVR instructions have a single 16-bit word format. Every program memory address con-
tains a 16- or 32-bit instruction.
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