AT43USB320A_04 Datasheet, PDF (61/115 Pages) ATMEL Corporation – Full-speed USB Microcontroller with an Embedded Hub

AT43USB320A
UART Control
UART I/O Data
Register – UDR
UART Status
Register – USR
Bit
$0D ($2C)
Read/Write
Initial Value
7
MSB
R/W
0
6
–
R/W
0
5
–
R/W
0
4
–
R/W
0
3
–
R/W
0
2
–
R/W
0
1
–
R/W
0
0
LSB
R/W
0
UDR
The UDR register is actually two physically separate registers sharing the same I/O address.
When writing to the register, the UART Transmit Data register is written. When reading from
UDR, the UART Receive Data register is read.
Bit
7
6
5
4
3
2
1
0
$0D ($2B)
RXC
TXC
UDRE
FE
OR
–
–
–
USR
Read/Write
R/W
R/W
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
The USR register is a read-only register providing information on the UART status.
• Bits 7 – RXC: UART Receive Complete
This bit is set (one) when a received character is transferred from the Receiver Shift register to
UDR. The bit is set regardless of any detected framing errors. When the RXCIE bit in UCR is
set, the UART Receive Complete interrupt will be executed when RXC is set (one). RXC is
cleared by reading UDR. When interrupt-driven data reception is used, the UART Receive
Complete Interrupt routine must read UDR in order to clear RXC, otherwise a new interrupt will
occur once the interrupt routine terminates.
• Bit 6 – TXC: UART Transmit Complete
This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift reg-
ister has been shifted out an d no new data has been written to UDR. This flag is especially
useful in half-duplex communications interfaces, where a transmitting application must enter
receive mode and free the communications bus immediately after completing the
transmission.
When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete inter-
rupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical "1"to the bit.
1443E–USB–4/04
• Bit 5 – UDRE: UART Data Register Empty
This bit is set (one) when a character written to UDR is transferred to the Transmit Shift regis-
ter. Setting of this bit indicates that the transmitter is ready to receive a new character for
transmission.
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