AT24C128B_14 Datasheet, PDF (7/23 Pages) ATMEL Corporation – Schmitt Trigger, Filtered Inputs for Noise Suppression

AT24C128B
cycles, (c) create another start bit followed by stop bit condition as shown below. The device is
ready for next communication after above steps have been completed.
Figure 6-3. Software Reset
Start bit
Dummy Clock Cycles
Start bit
Stop bit
SCL
1
2
3
8
9
SDA
Figure 6-4. Bus Timing
SCL
SDA IN
t_SU.STA
SDA OUT
Figure 6-5. Write Cycle Timing
SCL
t_F
t_LOW
t_HD.STA
t_HIGH
t_HD.DAT
t_LOW
t_SU.DAT
t_AA
t_DH
t_R
t_SU.STO
t_BUF
SDA
8th BIT
ACK
WORDn
STOP
CONDITION
(1)
t_wr
START
CONDITION
Note: 1. The write cycle time t_WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
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5296A–SEEPR–1/08