AT24C11_14 Datasheet, PDF (7/13 Pages) ATMEL Corporation – Low Voltage and Standard Voltage Operation

AT24C11
4. Write Operations
BYTE WRITE: Following a start condition, a write operation requires a 7-bit data word address
and a low write bit. Upon receipt of this address, the EEPROM will again respond with a zero
and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM
will output a zero and the addressing device, such as a microcontroller, must terminate the write
sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle
to the nonvolatile memory. All inputs are disabled during this write cycle, t_WR, and the EEPROM
will not respond until the write is complete (see refer to Figure 5-1 on page 8).
PAGE WRITE: The AT24C11 is capable of a 4-byte page write.
A page write is initiated the same as a byte write but the microcontroller does not send a stop
condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to three more data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must ter-
minate the page write sequence with a stop condition (see Figure 5-2 on page 8).
The data word address lower 2 bits are internally incremented following the receipt of each data
word. The higher five data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the fol-
lowing byte is placed at the beginning of the same page. If more than four data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten. Access to 1 additional page is available upon request.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond with
a zero allowing the read or write sequence to continue.
5. Read Operations
Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to one. There are two read operations:
byte read and sequential read.
BYTE READ: A byte read is initiated with a start condition followed by a 7-bit data word address
and a high read bit. The AT24C11 will respond with an acknowledge and then serially output 8
data bits. The microcontroller does not respond with a zero but does generate a following stop
condition (see Figure 5-3 on page 8).
SEQUENTIAL READ: Sequential reads are initiated the same as a byte read. After the micro-
controller receives an 8-bit data word, it responds with an acknowledge. As long as the
EEPROM receives an acknowledge, it will continue to increment the data word address and
serially clock out sequential data words. When the memory address limit is reached, the data
word address will “roll over” and the sequential read will continue. The sequential read operation
is terminated when the microcontroller does not respond with an input zero but does generate a
following stop condition (see Figure 5-4 on page 8).
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