AT24C11_14 Datasheet, PDF (5/13 Pages) ATMEL Corporation – Low Voltage and Standard Voltage Operation

AT24C11
STANDBY MODE: The AT24C11 features a low power standby mode which is enabled: (a)
upon power-up and (b) after the receipt of the STOP bit and the completion of any internal
operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part
can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create
a start condition as SDA is high.
Figure 3-1. Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
t_F
t_HIGH
t_R
SCL
t_LOW
t_LOW
SDA IN
t_SU.STA
t_HD.STA
t_HD.DAT
t_SU.DAT
t_SU.STO
t_AA
t_DH
t_BUF
SDA OUT
Figure 3-2. Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th BIT
ACK
WORDn
STOP
CONDITION
(1)
t_wr
START
CONDITION
Note: 1. The write cycle time t_WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
5
5093E–SEEPR–8/07