AT17F040A_14 Datasheet, PDF (7/16 Pages) ATMEL Corporation – In-System Programmable (ISP) via 2-wire Bus

AT17F040A/080A
6. FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration pro-
gram. The program is loaded either automatically upon power-up, or on command, depending
on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the config-
uration program from an external memory. The AT17FxxxA Serial Configuration PROM has
been designed for compatibility with the Master Serial mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as
Altera applications.
7. Control of Configuration
Most connections between the FPGA device and the AT17FxxxA Serial Configurator PROM are
simple and self-explanatory.
• The DATA output of the AT17FxxxA Series Configurator drives DIN of the FPGA devices.
• The DCLK output of the AT17FxxxA device drives the DCLK input data of the FPGA.
• The nCASC output of a AT17FxxxA Series Configurator drives the nCS input of the next
Configurator in a cascade chain of configurator devices.
• SER_EN must be at logic High level (internal pull-up resistor provided) except during ISP.
• The READY pin is available as an open-collector indicator of the device’s reset status; it is
driven Low while the device is in its power-on reset cycle and released (tri-stated) when the
cycle is complete.
• PAGE_EN must REMAIN Low if download paging is not desired. If paging is desired,
PAGE_EN must be High and the PAGESEL pins must be set to High or Low such that the
desired page is selected, see Table 5-2 on page 5.
8. Cascading Serial Configuration Devices
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration
memories, cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator asserts its
nCASC output Low and disables its DATA line driver. The second configurator recognizes the
Low level on its nCS input and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are reset if
the RESET/OE on each configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input can be
tied to its inactive (High) level.
9. Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can be pro-
grammed by the 2-wire serial bus. The programming is done at V_CC supply only. Programming
super voltages are generated inside the chip. The AT17FxxxA parts are read/write at 3.3V nom-
inal. Refer to the AT17FxxxA Programming Specification available on the Atmel web site
(www.atmel.com) for more programming details. AT17FxxxA devices are supported by the
Atmel ATDH2200 programming system along with many third party programmers.
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