AT17F040A_14 Datasheet, PDF (4/16 Pages) ATMEL Corporation – In-System Programmable (ISP) via 2-wire Bus

5. Pin Description
Table 5-1. Pin Description
Name
I/O
DATA
I/O
DCLK
I
PAGE_EN
I
PAGESEL0
I
PAGESEL1
I
RESET/OE
I
nCS
I
GND
–
nCASC
O
A2
I
READY
O
SER_EN
I
V_CC
–
AT17F040A/080A
20
PLCC
32
TQFP
2
31
4
2
16
21
11
14
7
6
8
7
9
10
10
12
12
15
15
20
18
23
20
27
5.1 DATA⁽¹⁾
Three-state DATA output for FPGA configuration. Open-collector bi-directional pin for configura-
tion programming.
5.2 DCLK⁽¹⁾
Three-state clock. Functions as an input when the Configurator is in programming mode (i.e.
SER_EN is Low) and as an output during FPGA configuration.
5.3 PAGE_EN⁽²⁾
Input used to enable page download mode. When PAGE_EN is high the configuration download
address space is partitioned into 4 equal pages. This gives users the ability to easily store and
retrieve multiple configuration bitstreams from a single configuration device. This input works in
conjunction with the PAGESEL inputs. PAGE_EN must be remain low if paging is not desired.
When SER_EN is Low (ISP mode) this pin has no effect.
Notes: 1. This pin has an internal 20 kΩ pull-up resistor.
2. This pin has an internal 30 kΩ pull-down resistor.
4 AT17F040A/080A
2823D–CNFG–2/08