AT89C5131A-L_14 Datasheet, PDF (69/186 Pages) ATMEL Corporation – Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode

AT89C5131A-L
SADDR - Slave Address Register (A9h)
7
6
5
4
3
2
1
0
Reset Value = 0000 0000b
Not bit addressable
Baud Rate Selection for
UART for Mode 1 and 3
The Baud Rate Generator for transmit and receive clocks can be selected separately via
the T2CON and BDRCON registers.
Figure 37. Baud Rate Selection
TIMER1
TIMER2
0
TIMER_BRG_RX
1
INT_BRG
RCLK
0
1
RBCK
/ 16
Rx Clock
TIMER1
TIMER2
INT_BRG
0
1
TCLK
TIMER_BRG_TX
0
1
TBCK
/ 16
Tx Clock
Baud Rate Selection Table for
UART
TCLK
(T2CON)
0
1
0
1
X
X
0
1
X
RCLK
(T2CON)
0
0
1
1
0
1
X
X
X
TBCK
(BDRCON)
0
0
0
0
1
1
0
0
1
RBCK
(BDRCON)
0
0
0
0
0
0
1
1
1
Clock Source
UART Tx
Timer 1
Timer 2
Timer 1
Timer 2
INT_BRG
INT_BRG
Timer 1
Timer 2
INT_BRG
Clock Source
UART Rx
Timer 1
Timer 1
Timer 2
Timer 2
Timer 1
Timer 2
INT_BRG
INT_BRG
INT_BRG
Internal Baud Rate Generator
(BRG)
When the internal Baud Rate Generator is used, the Baud Rates are determined by the
BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode)
in BDRCON register and the value of the SMOD1 bit in PCON register.
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4338F–USB–08/07