ARM7TDMI_14 Datasheet, PDF (68/284 Pages) ATMEL Corporation – Technical Reference Manual

Programmer’s Model
Address Exception
0x00000010 Data Abort
0x00000014 Reserved
0x00000018 IRQ
0x0000001C FIQ
Table 2-4 Exception vectors (continued)
Mode on entry I state on entry F state on entry
Abort
Set
Reserved
-
IRQ
Set
FIQ
Set
Unchanged
-
Unchanged
Set
2.8.10 Exception priorities
When multiple exceptions arise at the same time, a fixed priority system determines the
order in which they are handled. The priority order is listed in Table 2-5.
Table 2-5 Exception priority order
Priority Exception
Highest
Lowest
Reset
Data Abort
FIQ
IRQ
Prefetch Abort
Undefined instruction and SWI
Some exceptions cannot occur together:
• The undefined instruction and SWI exceptions are mutually exclusive. Each
corresponds to a particular, non-overlapping, decoding of the current instruction.
• When FIQs are enabled, and a Data Abort occurs at the same time as an FIQ, the
ARM7TDMI processor enters the Data Abort handler, and proceeds immediately
to the FIQ vector.
A normal return from the FIQ causes the Data Abort handler to resume execution.
Data Aborts must have higher priority than FIQs to ensure that the transfer error
does not escape detection. You must add the time for this exception entry to the
worst-case FIQ latency calculations in a system that uses aborts to support virtual
memory.
2-22
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