ARM7TDMI_14 Datasheet, PDF (215/284 Pages) ATMEL Corporation – Technical Reference Manual

Name
nRESET
Not reset
nRW
Not read, write
nTDOEN
Not TDO enable
nTRANS
Not memory translate
nTRST
Not test reset
nWAIT
Not wait
PCLKBS
Boundary scan
update clock
Signal Description
Table A-3 Signal Descriptions (continued)
Type Description
IC
Used to start the processor from a known address.
A LOW level causes the instruction being executed to terminate
abnormally.
This signal must be held LOW for at least two clock cycles, with nWAIT
held HIGH.
When LOW the processor performs internal cycles with the address
incrementing from the point where reset was activated. The address
overflows to zero if nRESET is held beyond the maximum address limit.
When HIGH for at least one clock cycle, the processor restarts from
address 0.
O8 When the processor is performing a read cycle, this is LOW.
This is one of the signals controlled by APE, ALE, and ABE.
O4 When serial data is being driven out on TDO this is LOW.
Usually used as an output enable for a TDO pin in a packaged part.
O8 When the processor is in User mode, this is LOW.
It can be used either to tell the memory management system when
address translation is turned on, or as an indicator of non-User mode
activity.
This is one of the signals controlled by APE, ALE, and ABE.
IC
Reset signal for the boundary-scan logic. This pin must be pulsed or
driven LOW to achieve normal device operation, in addition to the
normal device reset, nRESET.
See Chapter 5 Debug Interface.
IC
When LOW the processor extends an access over a number of cycles of
MCLK, which is useful for accessing slow memory or peripherals.
Internally, nWAIT is logically ANDed with MCLK and must only
change when MCLK is LOW.
If nWAIT is not used it must be tied HIGH.
O4 This is used by an external boundary-scan chain as the update clock.
This must be left unconnected, if an external boundary-scan chain is not
connected.
ARM DDI 0029G
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