AT91SAM7X512_1 Datasheet, PDF (675/687 Pages) ATMEL Corporation – AT91 ARM Thumb-based Microcontrollers

AT91SAM7X512/256/128 Preliminary
Version
6120F
(Continued) ^Comments
PIO:Section 27.4.4 “Output Control” on page 233, typo corrected
Section 27.4.1 “Pull-up Resistor Control” on page 233 reference to resistor value removed.
Figure 27-3 on page 232 0 and 1 inverted in the MUX controlled by PIO_MDSR..
Change
Request
Ref.
05-346
05-497
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SPI: Section 28.7.5 “SPI Status Register” on page 273 SPI_RCR, SPI_RNCR, SPI_TCR, SPI_TNCR
04-183
location defined.
Section 28.7.4 “SPI Transmit Data Register” on page 272, LASTXFER: Last Transfer text added.
05-434
Section 28.7.2 “SPI Mode Register” on page 269, PCSDEC: Chip Select Decode changed.
05-476
Updated Figure 28-1, ”Block Diagram” on page 256, removed Note. Removed bit FDIV from Section 28.7.2 ^05-484
“SPI Mode Register” on page 269 and Section 28.7.9 “SPI Chip Select Register” on page 278. LLB
description modified in Section 28.7.2 “SPI Mode Register” on page 269.
Updated Figure 28-9, ”Slave Mode Functional Block Diagram” on page 266 to remove FLOAD.
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Updated information on SPI_RDR in Section 28.6.3 “Master Mode Operations” on page 260. Added
information to SWRST bit description in Section 28.7.1 “SPI Control Register” on page 268. Corrected
equations in DLYBCT bit description, Section 28.7.9 ”SPI Chip Select Register” on page 279.
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Changes to Section 28.6.3.8 “Mode Fault Detection” on page 265.
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USART:
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Manchester Functionality Removed.
Section 30.4 “I/O Lines Description” on page 305, text concerning TXD line added.
Section 30.6.1.3 “Fractional Baud Rate in Asynchronous Mode” on page 309, using USART “functional
mode” changed to USART “normal mode”.
Table 30-3, “Binary and Decimal Values for Di,” on page 311 and Table 30-4, “Binary and Decimal Values
for Fi,” on page 311: DI and Fi properly referenced in titles.
Figure 30-25, ”IrDA Demodulator Operations” on page 327 modified.
Section 30.6.4.1 “ISO7816 Mode Overview” on page 323 clarification of PAR configuration added.
Section 30.6.7 “Modem Mode” on page 329 Control of DTR and RTS output pins.
Table 30-2, “Baud Rate Example (OVER = 0),” on page 308 60k and 70k MHz clock speeds removed.
“Asynchronous Receiver” on page 313 2nd line in 4th paragraph changed.
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“Receiver Time-out” on page 318 list of user options rewritten.
Section 30.7.1 ”USART Control Register” STTTO bit function related to TIMEOUT in US_CSR register
Section 30.7.6 ”USART Channel Status Register” TIMEOUT bit function related to STTO in US_CR register
TC: Section 32.5.12 “External Event/Trigger Conditions” on page 404 “....(EEVT = 0), TIOB is no longer
used as an output and the compare register B is not used to generate waveforms and subsequently no
IRQs. Note ⁽¹⁾ attached to ”EEVT: External Event Selection” in Section 32.6.5 “TC Channel Mode Register:
2704
Waveform Mode” on page 411 further clarifies this condition.
PWM: Section 33.5.3.3 ”Changing the Duty Cycle or the Period”: updated info on waveform generation. 1677
Section 34. “USB Device Port (UDP)” on page 441: Corrections, improvements, additions and deletions
throughout section, new source document.
Section 34.5.3.8 ”Sending a Device Remote Wakeup” replaces title “Sending an External Resume.
WAKEUP bit shown in interruput registers: Section 34.6.4 on page 470 thru Section 34.6.8 on page 476
RMWUPE, RSMINPR, ESR bits removed from Section 34.6.2 ”UDP Global State Register”
NOTE: pertinent to USB pullup effect on USB Reset added to Section 34.6.12 ”UDP Transceiver Control
Register”.
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6120H–ATARM–17-Feb-09
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