AT32UC3A3256S_2 Datasheet, PDF (656/1014 Pages) ATMEL Corporation – 32-bit AVR®Microcontroller

AT32UC3A3/A4
• The Received OUT Data Interrupt (RXOUTI)
• The Received SETUP Interrupt (RXSTPI)
• The Short Packet (SHORTPACKET) interrupt
• The Number of Busy Banks (NBUSYBK) interrupt
• The Received OUT isochronous Multiple Data Interrupt (MDATAI)
• The Received OUT isochronous DataX Interrupt (DATAXI)
The exception device endpoint interrupts are:
• The Underflow Interrupt (UNDERFI)
• The NAKed OUT Interrupt (NAKOUTI)
• The High-bandwidth isochronous IN error Interrupt (HBISOINERRI)
• The NAKed IN Interrupt (NAKINI)
• The High-bandwidth isochronous IN Flush error Interrupt (HBISOFLUSHI)
• The Overflow Interrupt (OVERFI)
• The STALLed Interrupt (STALLEDI)
• The CRC Error Interrupt (CRCERRI)
• The Transaction error (ERRORTRANS) interrupt
•DMA interrupts
The processing device DMA interrupts are:
• The End of USB Transfer Status (EOTSTA) interrupt
• The End of Channel Buffer Status (EOCHBUFFSTA) interrupt
• The Descriptor Loaded Status (DESCLDSTA) interrupt
There is no exception device DMA interrupt.
26.7.2.20
Test Modes
When written to one, the UDCON.TSTPCKT bit switches the USB device controller in a “test
packet”mode:
The transceiver repeatedly transmit the packet stored in the current bank. TSTPCKT must be
written to zero to exit the “test-packet” mode. The endpoint shall be reset by software after a
“test-packet” mode.
This enables the testing of rise and falling times, eye patterns, jitter, and any other dynamic
waveform specifications.
The flow control used to send the packets is as follows:
• TSTPCKT=1;
• Store data in an endpoint bank
• Write a zero to FifoCON bit
To stop the test-packet mode, just write a zero to the TSTPCKT bit.
32072C–AVR32–2010/03
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