AT32UC3A3256S_2 Datasheet, PDF (566/1014 Pages) ATMEL Corporation – 32-bit AVR®Microcontroller

AT32UC3A3/A4
Table 25-9. Maximum Time-out Period (Continued)
Baud Rate
Bit Time
56000
18
57600
17
200000
5
Time-out
1 170
1 138
328
25.6.3.12
Framing Error
The receiver is capable of detecting framing errors. A framing error happens when the stop bit of
a received character is detected at level 0. This can occur if the receiver and the transmitter are
fully desynchronized.
A framing error is reported on the FRAME bit of the Channel Status Register (CSR). The
FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is
cleared by writing the Control Register (CR) with the RSTSTA bit at 1.
Figure 25-24. Framing Error Status
Baud Rate
Clock
RXD
Write
CR
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
RSTSTA = 1
FRAME
RXRDY
25.6.3.13
Transmit Break
The user can request the transmitter to generate a break condition on the TXD line. A break con-
dition drives the TXD line low during at least one complete character. It appears the same as a
0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the
TXD line at least during one character until the user requests the break condition to be removed.
A break is transmitted by writing the Control Register (CR) with the STTBRK bit at 1. This can be
performed at any time, either while the transmitter is empty (no character in either the Shift Reg-
ister or in THR) or when a character is being transmitted. If a break is requested while a
character is being shifted out, the character is first completed before the TXD line is held low.
Once STTBRK command is requested further STTBRK commands are ignored until the end of
the break is completed.
The break condition is removed by writing CR with the STPBRK bit at 1. If the STPBRK is
requested before the end of the minimum break duration (one character, including start, data,
parity and stop bits), the transmitter ensures that the break condition completes.
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