TSC80251G2D Datasheet, PDF (64/76 Pages) ATMEL Corporation – B/16-BIT MICROCONTROLLER WITH SERIAL COMMUNICATION INTERFACES

Notes: 1. Under steady-state (non-transient) conditions, I_OL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:Port 0 26 mA
Ports 1-3 15 mA
Maximum Total IOL for all: Output Pins 71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test
conditions.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports
1, 2, and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change
from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
3. Capacitive loading on Ports 0 and 2 causes the V_OH on ALE and PSEN# to drop below the specification when the address
lines are stabilizing.
4. Typical values are obtained using V_DD = 5 V and T_A = 25°C. They are not tested and there is not guarantee on these values.
5. The input threshold voltage of SCL and SDA meets the TWI specification, so an input voltage below 0.3·V_DD will be recog-
nized as a logic 0 while an input voltage above 0.7·V_DD will be recognized as a logic 1.
Figure 28. I_DD/I_DL Versus Frequency; V_DD = 4.5 to 5.5 V
40
30
20
10
0
2
4
max Active mode (mA)
typ Active mode (mA)
max Idle mode (mA)
typ Idle mode (mA)
6
8 10 12 14 16 18 20 22 24
Frequency at XTAL(1) (MHz)
Note: 1. The clock prescaler is not used: F_OSC = F_XTAL.
64 AT/TSC8x251G2D
4135D–8051–08/05