SAM7S32_14 Datasheet, PDF (603/775 Pages) ATMEL Corporation – Internal High-speed Flash

40.4.6.3 SPI: LASTXFER (Last Transfer) Behavior
In FIXED Mode, with CSAAT bit set, and in “PDC mode” the Chip Select can rise depending on the data written in
the SPI_TDR when the TX_EMPTY flag is set. If for example, the PDC writes a “1” in the bit 24 (LASTXFER bit) of
the SPI_TDR, the chip select will rise as soon as the TXEMPTY flag is set.
Problem Fix/Workaround
Use the CS in PIO mode when PDC mode is required and CS has to be maintained between transfers.
40.4.6.4 SPI: SPCK Behavior in Master Mode
SPCK pin can toggle out before the first transfer in Master Mode.
Problem Fix/Workaround
In Master Mode, MSTR bit must be set (in SPI_MR register) before configuring SPI_CSRx registers.
40.4.6.5 SPI: Chip Select and Fixed Mode
In fixed Mode, if a transfer is performed through a PDC on a Chip select different from the Chip select 0, the output
spi_size sampled by the PDC will depend on the field, BITS (Bits per Transfer) of SPI_CSR0 register, whatever the
selected Chip select is. For example, if SPI_CSR0 is configured for a 10-bit transfer whereas SPI_CSR1 is config-
ured for an 8-bit transfer, when a transfer is performed in Fixed mode through the PDC, on Chip select 1, the
transfer will be considered as a HalfWord transfer.
Problem Fix/Workaround
If a PDC transfer has to be performed in 8 bits, on a Chip select y (y as different from 0), the BITS field of the
SPI_CSR0 must be configured in 8 bits, in the same way as the BITS field of the CSRy Register.
40.4.6.6 SPI: Baudrate Set to 1
When Baudrate is set at 1 (i.e. when serial clock frequency equals the system clock frequency) and when the BITS
field of the SPI_CSR register (number of bits to be transmitted) equals an ODD value (in this case 9,11,13 or 15),
an additional pulse will be generated on output SPCK.
Everything is OK if the BITS field equals 8,10,12,14 or 16 and Baudrate = 1.
Problem Fix/Workaround
None.
40.4.6.7 SPI: Disable In Slave Mode
The SPI disable is not possible in slave mode.
Problem Fix/Workaround
Read first the received data, then perform the software reset.
40.4.6.8 SPI: Bad Serial Clock Generation on 2nd Chip Select
Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0.
This occurs using SPI with the following conditions:
• Master Mode
• CPOL = 1 and NCPHA = 0
• Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when serial clock
frequency equals the system clock frequency) and the other transfers set with SCBR are not equal to 1
• Transmitting with the slowest chip select and then with the fastest one, then an additional pulse is generated
on output SPCK during the second transfer.
Problem Fix/Workaround
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
603