AT24C256SC_14 Datasheet, PDF (6/13 Pages) ATMEL Corporation – Schmitt Trigger, Filtered Inputs for Noise Suppression

Timing Diagrams
Bus Timing
Figure 3. Bus Timing
Write Cycle Timing
Note: SCL: Serial Clock; SDA: Serial Data I/O
Figure 4. Write Cycle Timing
Data Validity
t_WR(1)
Note:
1. The write cycle time t_WR is the time from a valid stop condition of a write sequence to
the end of the internal clear/write cycle.
SCL: Serial Clock; SDA: Serial Data I/O
Figure 5. Data Validity
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
6 AT24C128SC/AT24C256SC
1661B–SEEPR–04/04