SAM7X512_14 Datasheet, PDF (595/662 Pages) ATMEL Corporation – ARM-based Flash MCU

Figure 38-7. SPI Slave mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1)
SPCK
MISO
MOSI
SPI₉
SPI₁₀
SPI₁₁
Table 38-21. SPI Timings
Symbol
Parameter
Conditions
Min
SPI₀
SPI₁
SPI₂
SPI₃
SPI₄
SPI₅
SPI₆
SPI₇
SPI₈
SPI₉
SPI₁₀
SPI₁₁
MISO Setup time before SPCK rises (master)
MISO Hold time after SPCK rises (master)
SPCK rising to MOSI Delay (master)
MISO Setup time before SPCK falls (master)
MISO Hold time after SPCK falls (master)
SPCK falling to MOSI Delay (master)
SPCK falling to MISO Delay (slave)
MOSI Setup time before SPCK rises (slave)
MOSI Hold time after SPCK rises (slave)
SPCK rising to MISO Delay (slave)
MOSI Setup time before SPCK falls (slave)
MOSI Hold time after SPCK falls (slave)
3.3V domain⁽¹⁾
3.3V domain⁽¹⁾
3.3V domain⁽¹⁾
3.3V domain⁽¹⁾
3.3V domain ⁽¹⁾
3.3V domain ⁽¹⁾
3.3V domain ⁽¹⁾
3.3V domain ⁽¹⁾
3.3V domain ⁽¹⁾
3.3V domain ⁽¹⁾
3.3V domain ⁽¹⁾
3.3V domain ⁽¹⁾
28.5 + (t_CPMCK)/2⁽²⁾
0
26.5 + (t_CPMCK)/2⁽²⁾
0
2
3
3
3
Notes: 1. 3.3V domain: V_VDDIO from 3.0V to 3.6V, maximum external capacitor = 40 pF.
2. t_CPMCK: Master Clock period in ns.
Max
2
2
28
28
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note that in SPI master mode the ATSAM7X512/256/128 does not sample the data (MISO) on the opposite edge where
data clocks out (MOSI) but the same edge is used as shown in Figure 38-4 and Figure 38-5.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
595