SAM7X512_14 Datasheet, PDF (170/662 Pages) ATMEL Corporation – ARM-based Flash MCU

24.4
Divider and PLL Block
The PLL embeds an input divider to increase the accuracy of the resulting clock signals. However, the user must respect
the PLL minimum input frequency when programming the divider.
Figure 24-3 shows the block diagram of the divider and PLL block.
Figure 24-3. Divider and PLL Block Diagram
DIV
MUL OUT
MAINCK
Divider
PLL
PLLCK
SLCK
PLLRC
PLLCOUNT
PLL
Counter
LOCK
24.4.1 PLL Filter
The PLL requires connection to an external second-order filter through the PLLRC pin. Figure 24-4 shows a schematic of
these filters.
Figure 24-4. PLL Capacitors and Resistors
PLLRC
PLL
R
C2
C1
GND
Values of R, C1 and C2 to be connected to the PLLRC pin must be calculated as a function of the PLL input frequency,
the PLL output frequency and the phase margin. A trade-off has to be found between output signal overshoot and startup
time.
24.4.2 Divider and Phase Lock Loop Programming
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the
corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the
corresponding PLL input clock is set to 0.
The PLL allows multiplication of the divider’s outputs. The PLL clock signal has a frequency that depends on the
respective source signal frequency and on the parameters DIV and MUL. The factor applied to the source signal
frequency is (MUL + 1)/DIV. When MUL is written to 0, the corresponding PLL is disabled and its power consumption is
saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field.
Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK bit in PMC_SR is automatically cleared.
The values written in the PLLCOUNT field in CKGR_PLLR are loaded in the PLL counter. The PLL counter then
decrements at the speed of the Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger
an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the PLL transient
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
170