TSC80251G2D_14 Datasheet, PDF (56/77 Pages) ATMEL Corporation – Registers Accessible as Bytes, Words or Dwords

Timings
Table 49. SPI Interface AC Timing; V_DD = 2.7 to 5.5 V, T_A = -40 to 85°C
Symbol Parameter
Min
Max
Slave Mode⁽¹⁾
T_CHCH
Clock Period
8
T_CHCX
Clock High Time
3.2
T_CLCX
Clock Low Time
3.2
T_SLCH, T_SLCL SS# Low to Clock edge
200
T_IVCL, T_IVCH Input Data Valid to Clock Edge
100
T_CLIX, T_CHIX Input Data Hold after Clock Edge
100
T_CLOV, T_CHOV Output Data Valid after Clock Edge
100
T_CLOX, T_CHOX Output Data Hold Time after Clock Edge
0
T_CLSH, T_CHSH SS# High after Clock Edge
0
T_IVCL, T_IVCH Input Data Valid to Clock Edge
100
T_CLIX, T_CHIX Input Data Hold after Clock Edge
100
T_SLOV
SS# Low to Output Data Valid
130
T_SHOX
Output Data Hold after SS# High
130
T_SHSL
SS# High to SS# Low
(2)
T_ILIH
Input Rise Time
2
T_IHIL
Input Fall Time
2
T_OLOH
Output Rise time
100
T_OHOL
Output Fall Time
100
Master Mode⁽³⁾
T_CHCH
Clock Period
4
T_CHCX
Clock High Time
1.6
T_CLCX
Clock Low Time
1.6
T_IVCL, T_IVCH Input Data Valid to Clock Edge
50
T_CLIX, T_CHIX Input Data Hold after Clock Edge
50
T_CLOV, T_CHOV Output Data Valid after Clock Edge
65
T_CLOX, T_CHOX Output Data Hold Time after Clock Edge
0
T_ILIH
Input Data Rise Time
2
T_IHIL
Input Data Fall Time
2
T_OLOH
Output Data Rise time
50
T_OHOL
Output Data Fall Time
50
Notes: 1. Capacitive load on all pins = 200 pF in slave mode.
2. The value of this parameter depends on software.
3. Capacitive load on all pins = 100 pF in master mode.
Unit
T_OSC
T_OSC
T_OSC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
ns
ns
T_OSC
T_OSC
T_OSC
ns
ns
ns
ns
μs
μs
ns
ns
56 AT/TSC8x251G2D
4135F–8051–11/06