TSC80251G2D_14 Datasheet, PDF (25/77 Pages) ATMEL Corporation – Registers Accessible as Bytes, Words or Dwords

AT/TSC8x251G2D
4. If this instruction addresses external memory location, add 2(N+2) to the number of
states (N: number of wait states).
Table 21. Summary of Increment and Decrement Instructions
IncrementINC <dest>dest opnd ← dest opnd + 1
IncrementINC <dest>, <src>dest opnd ← dest opnd + src opnd
DecrementDEC <dest>dest opnd ← dest opnd - 1
DecrementDEC <dest>, <src>dest opnd ← dest opnd - src opnd
Mnemonic
<dest>,
<src>⁽¹⁾
Comments
Binary Mode Source Mode
Bytes States Bytes States
A
ACC by 1
1
1
1
1
Rn
Register by 1
1
1
2
2
INC
DEC
dir8
Direct address (on-chip RAM or
SFR) by 1
2
2⁽²⁾
2
2⁽²⁾
at Ri
Indirect address by 1
1
3
2
4
INC
DEC
Rm, #short
WRj, #short
Byte register by 1, 2, or 4
Word register by 1, 2, or 4
3
2
2
1
3
2
2
1
INC
DRk, #short Double word register by 1, 2, or 4
3
4
2
3
DEC
DRk, #short Double word register by 1, 2, or 4
3
5
2
4
INC
DPTR
Data pointer by 1
1
1
1
1
Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states.
Add 3 if it addresses a Peripheral SFR.
25
4135F–8051–11/06