TSC80251G2D_06 Datasheet, PDF (54/77 Pages) ATMEL Corporation – 8/16-bit Microcontroller with Serial Communication Interfaces

AC Characteristics - SSLC: TWI Interface
Timings
Waveforms
Table 47. TWI Interface AC Timing; V_DD = 2.7 to 5.5 V, T_A = -40 to 85°C
Symbol Parameter
INPUT
Min
Max
OUTPUT
Min
Max
THD; STA Start condition hold time
14·TCLCL(4)
4.0 μs⁽¹⁾
TLOW
SCL low time
16·TCLCL(4)
4.7 μs⁽¹⁾
THIGH
SCL high time
14·TCLCL(4)
4.0 μs⁽¹⁾
TRC
SCL rise time
TFC
SCL fall time
1 μs
0.3 μs
-⁽²⁾
0.3 μs⁽³⁾
TSU; DAT1 Data set-up time
250 ns
20·TCLCL(4)- TRD
TSU; DAT2
SDA set-up time (before repeated START
condition)
250 ns
1 μs⁽¹⁾
TSU; DAT3 SDA set-up time (before STOP condition)
THD; DAT Data hold time
250 ns
0 ns
8·TCLCL(4)
8·TCLCL(4) - TFC
TSU; STA Repeated START set-up time
14·TCLCL(4)
4.7 μs⁽¹⁾
TSU; STO
TBUF
TRD
TFD
STOP condition set-up time
Bus free time
SDA rise time
SDA fall time
14·TCLCL(4)
14·TCLCL(4)
1 μs
0.3 μs
4.0 μs⁽¹⁾
4.7 μs⁽¹⁾
-⁽²⁾
0.3 μs⁽³⁾
Notes:
1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of
100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-up
resistor, this must be < 1 μs.
3. Spikes on the SDA and SCL lines with a duration of less than 3·TCLCL will be filtered
out. Maximum capacitance on bus-lines SDA and
SCL = 400 pF.
4. TCLCL = T_OSC = one oscillator clock period.
Figure 18. TWI Waveforms
START or Repeated START condition
SDA
(INPUT/OUTPUT)
SCL
(INPUT/OUTPUT)
TRD
TFD
TRC
TFC
THD;STA TLOW THIGH TSU;DAT1 THD;DAT
Repeated START condition
STOP condition
TSU;STA
START condition
TSU;STO
TSU;DAT3
TBUF
0.7 V_DD
0.3 V_DD
0.7 V_DD
0.3 V_DD
TSU;DAT2
54 AT/TSC8x251G2D
4135F–8051–11/06