TSC80251G2D_06 Datasheet, PDF (18/77 Pages) ATMEL Corporation – 8/16-bit Microcontroller with Serial Communication Interfaces

Table 11. Configuration Byte 0
UCONFIG0
7
6
5
4
3
-
WSA1#
WSA0#
XALE#
RD1
2
RD0
1
PAGE#
0
SRC
Bit
Bit Number Mnemonic Description
7
-
Reserved
Set this bit when writing to UCONFIG0.
6
WSA1# Wait State A bits
Select the number of wait states for RD#, WR# and PSEN# signals for external
memory accesses (all regions except 01:).
WSA1# WSA0# Number of Wait States
5
WSA0# ⁰
0
3
0
1
2
1
0
1
1
1
0
Extend ALE bit
4
XALE# Clear to extend the duration of the ALE pulse from T_OSC to 3·T_OSC.
Set to minimize the duration of the ALE pulse to 1·T_OSC.
3
RD1 Memory Signal Select bits
Specify a 18-bit, 17-bit or 16-bit external address bus and the usage of RD#,
2
RD0 WR# and PSEN# signals (see Table 13).
Page Mode Select bit⁽¹⁾
Clear to select the faster Page mode with A15:8/D7:0 on Port 2 and A7:0 on
1
PAGE# Port 0.
Set to select the non-Page mode⁽²⁾ with A15:8 on Port 2 and A7:0/D7:0 on Port
0.
Source Mode/Binary Mode Select bit
0
SRC Clear to select the binary mode.
Set to select the source mode.
Notes:
1. UCONFIG0 is fetched twice so it can be properly read both in Page or Non-Page
modes. If P2.1 is cleared during the first data fetch, a Page mode configuration is
used, otherwise the subsequent fetches are performed in Non-Page mode.
2. This selection provides compatibility with the standard 80C51 hardware which is mul-
tiplexing the address LSB and the data on Port 0.
18 AT/TSC8x251G2D
4135F–8051–11/06