ATA8742_14 Datasheet, PDF (54/215 Pages) ATMEL Corporation – Microcontroller with UHF ASK/FSK Transmitter

16.8
Watchdog Timer
The watchdog timer is clocked from an on-chip oscillator which runs at 128kHz. By controlling the watchdog timer prescaler,
the watchdog reset interval can be adjusted as shown in Table 16-4 on page 57. The WDR – watchdog reset – instruction
resets the watchdog timer. The watchdog timer is also reset when it is disabled and when a chip reset occurs. Ten different
clock cycle periods can be selected to determine the reset period. If the reset period expires without another watchdog reset,
the Atmel^® ATtiny24/44/84 resets and executes from the reset vector. For timing details on the watchdog reset, refer to Table
16-4 on page 57.
The watchdog timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using
the watchdog to wake-up from power-down.
To prevent unintentional disabling of the watchdog or unintentional change of time-out period, two different safety levels are
selected by the fuse WDTON as shown in Table 16-2. See Section 16.9 “Timed Sequences for Changing the Configuration
of the Watchdog Timer” on page 54 for details.
Table 16-2. WDT Configuration as a Function of the Fuse Settings of WDTON
WDTON
Unprogrammed
Programmed
Safety Level
1
2
WDT Initial State
Disabled
Enabled
How to Disable the WDT
Timed sequence
Always enabled
How to Change Time-out
No limitations
Timed sequence
Figure 16-7. Watchdog Timer
128kHz
Oscillator
Watchdog
Prescaler
Watchdog
Reset
WDP0
WDP1
WDP2
WDP3
WDE
MCU Reset
16.9
Timed Sequences for Changing the Configuration of the Watchdog Timer
The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described
for each level.
16.9.1 Safety Level 1
In this mode, the watchdog timer is initially disabled, but can be enabled by writing the WDE bit to one without any restriction.
A timed sequence is needed when disabling an enabled watchdog timer. To disable an enabled watchdog timer, the
following procedure must be followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE regardless of the
previous value of the WDE bit.
2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as desired, but with the
WDCE bit cleared.
54 ATA8742 [DATASHEET]
9151C–INDCO–09/14