ATA5823_14 Datasheet, PDF (53/82 Pages) ATMEL Corporation – UHF ASK/FSK Transceiver

11.1.7 Receiving Mode
If the Bit-check was successful for all bits specified by N_Bit-check, the transceiver switches to receiving mode. To activate a
connected microcontroller, bit CLK_ON in control register 3 is set to 1. An interrupt is issued at pin IRQ if the control bits
T_MODE = 0 and P_MODE = 0.
If the transparent mode is active (T_MODE = 1) and the level on pin CS is inactive (no data transfer via the serial interface),
the RX data stream is available on pin SDO_TMDO (Figure 11-7).
Figure 11-7. Receiving Mode (TMODE = 1)
Preburst
Bit check ok
Start
bit
Byte 1
Byte 2
Byte 3
Demod_Out
'0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '0' '1' '0' '0' '0' '0' '0' '1' '1' '1' '1' '0' '0' '1' '1' '0' '1' '0' '1' '1' '0' '0'
SDO_TMDO
Bit-check mode
Receiving mode
If the transparent mode is inactive (T_MODE = 0), the received data stream is buffered in the TX/RX data buffer (see
Figure 11-8 on page 54). The TX/RX data buffer is only usable for Manchester and Bi-phase coded signals. It is permanently
possible to transfer the data from the data buffer via the 4-wire serial interface to a microcontroller (see Figure 10-1 on page
43).
Buffering of the data stream:
After a successful Bit-check, the transceiver switches from Bit-check mode to receiving mode. In receiving mode the TX/RX
data buffer control logic is active and examines the incoming data stream. This is done, like in the Bit-check, by subsequent
time frame checks where the distance between two edges is continuously compared to a programmable time window as
illustrated in Figure 11-8 on page 54. Only two distances between two edges in Manchester and Bi-phase coded signals are
valid (T and 2T).
The limits for T are the same as used for the Bit-check. They can be programmed in control register 5 and 6 (Lim_min,
Lim_max).
The limits for 2T are calculated as follows:
Lower limit of 2T:
Lim_min_2T = (Lim_min + Lim_max) – (Lim_max – Lim_min) ⁄ 2
T_{Lim_min_2T} = Lim_min_2T × T_XDCLK
Upper limit of 2T:
Lim_max_2T = (Lim_min + Lim_max) + (Lim_max – Lim_min) ⁄ 2
T_{Lim_max_2T} = (Lim_max_2T – 1 ) × T_XDCLK
If the result of Lim_min_2T or Lim_max_2T is not an integer value, it will be round up.
If the TX/RX data buffer control logic detects the start bit, the data stream is written in the TX/RX data buffer byte by byte.
The start bit is part of the first data byte and must be different from the bits of the preburst. If the preburst consists of a
sequence of “00000...”, the start bit must be a 1. If the preburst consists of a sequence of “11111...”, the start bit must be a 0.
If the data stream consists of more than 16 bytes, a buffer overflow occurs and the TX/RX data buffer control logic overwrites
the bytes already stored in the TX/RX data buffer. So it is very important to ensure that the data is read in time so that no
buffer overflow occurs in that case (see Figure 10-1 on page 43). There is a counter that indicates the number of received
bytes in the TX/RX data buffer (see section “Transceiver Configuration” on page 43). If a byte is transferred to the
microcontroller, the counter is decremented, if a byte is received, the counter is incremented. The counter value is available
via the 4-wire serial interface.
An interrupt is issued if the counter while counting forwards reaches the value defined by the control bits IR0 and IR1 in
control register 1.
ATA5823/ATA5824 [DATASHEET]
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