ATA5823_14 Datasheet, PDF (40/82 Pages) ATMEL Corporation – UHF ASK/FSK Transceiver

9.3.9
Status Register (ADR 16)
The status register indicates the current status of the transceiver and is readable via the 4-wire serial interface. Setting
Power_On or an event on N_Power_On is indicated by an IRQ.
Reading the status register resets the bits Power_On, DVCC_RST and the IRQ.
Table 9-26. Status Register
Status Bit
Function
N_Power_On
Power_On
Status of pin N_PWR_On
Pin N_PWR_ON = 0 → N_Power_On = 1
Pin N_PWR_ON = 1 → N_Power_On = 0
(Figure 9-3 on page 41)
Indicates that the transceiver was woken up by pin PWR_ON (rising edge on pin PWR_ON). During
Power_On = 1, the bit CLK_ON in control register 3 is set to 1 (Figure 9-4 on page 42).
DVCC_RST is set to 1 if the supply voltage of the RAM (V_DVCC) was too low and the information in
the RAM may be lost.
DVCC_RST
DVCC_RST = 0 → supply voltage of the RAM ok
DVCC_RST = 1 → supply voltage of the RAM was too low (typically V_DVCC < 1.6V)
If the transceiver changes from OFF mode to IDLE mode, DVCC_RST will be set to 1. Reading the
Status register resets DVCC_RST to 0.
9.4 Pin N_PWR_ON
To switch the transceiver from OFF to IDLE mode, pin N_PWR_ON must be set to 0 (maximum 0.2 × V_VS2) for at least
T_{N_PWR_ON_IRQ} (see Figure 9-2). The transceiver recognizes the negative edge and switches on DVCC and AVCC.
If V_DVCC exceeds 1.6V (typically) and the XTO is settled, the digital control logic is active and sets the status bit N_Power_On
to 1, an interrupt is issued (T_{N_PWR_ON_IRQ}) and the output clock on pin CLK is available.
If the level on pin N_PWR_ON was set to 1 before the interrupt is issued, the transceiver stays in OFF mode.
Note:
It is not possible to set the transceiver to OFF-mode by setting pin N_PWR_ON to 1. If pin N_PWR_ON is not
used, it should be left open because of the internal pull-up resistor
Figure 9-2. Timing Pin N_PWR_ON, Status Bit N_Power_On
N_PWR_ON
1.6V (typ)
DVCC, AVCC
CLK
N_POWER_ON
(Status register)
T_{N_PWR_ON_IRQ}
IRQ
OFF Mode
IDLE Mode
If the transceiver is in any of the active modes (IDLE, TX, RX, RX_Polling, FD), an integrated debounce logic is active. If
there is an event on pin N_PWR_ON, a debounce counter is set to 0 (T = 0) and started. The status is updated, an interrupt
is issued and the debounce counter is stopped after reaching the counter value T = 8195 × T_DCLK.
40 ATA5823/ATA5824 [DATASHEET]
4829F–RKE–05/14