AT91RM9200_05 Datasheet, PDF (517/683 Pages) ATMEL Corporation – ARM920T based Microcontroller

AT91RM9200
27. MultiMedia Card Interface (MCI)
27.1 Overview
The MultiMedia Card Interface (MCI) supports the MultiMedia Card (MMC) Specification V2.2
and the SD Memory Card Specification V1.0.
The MCI includes a command register, response registers, data registers, timeout counters and
error detection logic that automatically handle the transmission of commands and, when
required, the reception of the associated responses and data with limited processor overhead.
The MCI supports stream, block and multi-block data read and write, and is compatible with the
Peripheral DMA Controller channels, minimizing processor intervention for large buffer transfers.
The MCI operates at a rate of up to Master Clock divided by 2 and supports interfacing of up to
16 slots (depending on the product). Each slot may be used to interface with a MultiMedia Card
bus (up to 30 Cards) or with an SD Memory Card. Only one slot can be selected at a time (slots
are multiplexed). A bit in the Command Register performs this selection.
The SD Memory Card communication is based on a 9-pin interface (clock, command, four data
and three power lines) and the MultiMedia Card on a 7-pin interface (clock, command, one data
and three power lines).
The SD Memory Card interface also supports MultiMedia Card operations. The main differences
between SD and MultiMedia Cards are the initialization process and the bus topology.
The main features of the MCI are:
• Compatibility with MultiMedia Card Specification Version 2.2
• Compatibility with SD Memory Card Specification Version 1.0
• Cards clock rate up to Master Clock divided by 2
• Embedded power management to slow down clock rate when not used
• Supports up to sixteen multiplexed slots (product-dependent)
– One slot for one MultiMedia Card bus (up to 30 cards) or one SD Memory Card
• Support for stream, block and multi-block data read and write
• Supports connection to Peripheral DMA Controller
– Minimizes processor intervention for large buffer transfers
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