ATTINY88 Datasheet, PDF (51/246 Pages) ATMEL Corporation – High Endurance Non-volatile Memory Segments

ATtiny88 Automotive
9.3 Register Description
9.3.1
EICRA – External Interrupt Control Register A
The External Interrupt Control Register A contains control bits for interrupt sense control.
Bit
7
6
5
4
3
2
1
0
–
–
–
–
ISC11
ISC10
ISC01
ISC00
EICRA
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bits 7..4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT1 pin that activate the
interrupt are defined in Table 9-2. The value on the INT1 pin is sampled before detecting edges.
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
Table 9-2.
ISC11
0
0
1
1
Interrupt 1 Sense Control
ISC10 Description
0
The low level of INT1 generates an interrupt request.
1
Any logical change on INT1 generates an interrupt request.
0
The falling edge of INT1 generates an interrupt request.
1
The rising edge of INT1 generates an interrupt request.
• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in Table 9-3. The value on the INT0 pin is sampled before detecting edges.
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
Table 9-3.
ISC01
0
0
1
1
Interrupt 0 Sense Control
ISC00 Description
0
The low level of INT0 generates an interrupt request.
1
Any logical change on INT0 generates an interrupt request.
0
The falling edge of INT0 generates an interrupt request.
1
The rising edge of INT0 generates an interrupt request.
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