ATTINY88 Datasheet, PDF (127/246 Pages) ATMEL Corporation – High Endurance Non-volatile Memory Segments

ATtiny88 Automotive
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see Table 14-5). This means that the minimum SCK period will be two CPU
clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f_osc/4
or lower.
The SPI interface on the ATtiny88 is also used for program memory and EEPROM downloading
or uploading. See page 203 for serial programming and verification.
14.5.3 SPDR – SPI Data Register
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
MSB
LSB
SPDR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
Undefined
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-
ter causes the Shift Register Receive buffer to be read.
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