AT91CAP9SC500A Datasheet, PDF (50/60 Pages) ATMEL Corporation – Customizable Microcontroller Processor

• Embedded 6 channels DMA controller
• Suspend/Resume logic
• Up to 2 or 3 banks for isochronous and bulk endpoints
• Seven endpoints:
– Endpoint 0: 64 bytes
– Endpoint 1 & 2: 1024 bytes, 3 banks mode, HS isochronous capable
– Endpoint 3 & 4: 1024 bytes, 2 banks mode, HS isochronous capable
– Endpoint 5 & 6: 1024 bytes, 2 banks mode
– Endpoint 7: 1024 bytes, 2 banks mode
10.4.14
LCD Controller
• Single and Dual scan color and monochrome passive STN LCD panels supported
• Single scan active TFT LCD panels supported
• 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported
• Up to 24-bit single scan TFT interfaces supported
• Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays
• 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN
• 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN
• 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT
• Single clock domain architecture
• Resolution supported up to 2048x2048
• 2D-DMA Controller for management of virtual Frame Buffer
– Allows management of frame buffer larger than the screen size and moving the view
over this virtual frame buffer
• Automatic resynchronization of the frame buffer pointer to prevent flickering
10.4.15
Ethernet 10/100 MAC
• Compatibility with IEEE Standard 802.3
• 10 and 100 MBits per second data throughput capability
• Full- and half-duplex operations
• MII or RMII interface to the physical layer
• Register Interface to address, data, status and control registers
• Internal DMA Controller, operating as a Master on Bus Matrix
• Interrupt generation to signal receive and transmit completion
• 28-byte transmit and 28-byte receive FIFOs
• Automatic pad and CRC generation on transmitted frames
• Address checking logic to recognize four 48-bit addresses
• Support promiscuous mode where all valid frames are copied to memory
• Support physical layer management through MDIO interface control of alarm and update
time/calendar data in
50 AT91CAP9SC500A/AT91CAP9SC250A Preliminary
6270AS–CAP–10-Jan-08