TH7899M Datasheet, PDF (5/24 Pages) ATMEL Corporation – Full Field CCDImage Sensor 2048 x 20Pixels48

TH7899M
Horizontal Registers
The sensor has two readout registers located at the top (register A) and at the bottom
(register B) of the image area. They can be driven independently by two phase clocks.
Nevertheless to allow a multiple charge transfer direction for the useful pixels (left, right
or half left and half right), the two clocks are split into 6 clocks (ΦLA_{i=1 to 6} for the A regis-
ter and ΦLB_{i=1 to 6} for the register B). The transfer direction is fixed by the connection
mode of the six clocks into 2 clocks.
The description of the connection with the transfer direction is described in “” on page 9.
The readout register has 2072 stages, with a further 18 extra stages at each end. What-
ever the chosen transfer direction for the useful pixels, the 18 extra pixels, the 7 dark
references and the 5 isolations are always transferred to the nearest output as shown in
the figure hereunder.
Figure 4. A and B Readout Register Structure
Binned Modes
The readout register can be driven in the MPP mode if necessary.
Two types of summation can be performed:
• Vertical summation in each stage of the serial register (A or B)
• Horizontal summation in an output summing well driven by ΦS clock and located at
each end of the readout registers (A and B).
Nevertheless, one summation can be performed in both the register and the output sum-
ming, allowing in this way, to have a resulting signal of (2 x 2) contiguous pixels from the
image area. Thus, the sensor is equivalent to a 1024 x 1024 array of a 28 µm x 28 µm
pixel. When using the binned mode with a charge level, after summation, smaller than
300 ke- (typical value) it is better (optimization of dynamic and linearity) to keep the con-
version factor at 7 µV/e- (with VGL = 1V and VDR = 13.5V). But for summing mode with
charge level, after binning, higher than 300 ke-, the conversion factor should be reduced
by increasing the VGL gate to 12V and the VDR reset drain to 15V. With such a method,
the saturation charge is optimized for the binning mode.
This summing technique leads to an increased signal to noise ratio, larger pixel size,
higher frame rates (for vertical binning only) but at the expense of a loss in resolution.
5
2201A–IMAGE–02/02