ATTINY441_14 Datasheet, PDF (47/366 Pages) ATMEL Corporation – 8-bit AVR Microcontroller with 4/8K Bytes In-System

8.5.2 WDTCSR – Watchdog Timer Control and Status Register
Bit
0x21 (0x41)
Read/Write
Initial Value
7
6
5
4
WDIF
WDIE
WDP3
–
R/W
R/W
R/W
R/W
0
0
0
0
3
WDE
R/W
X
2
WDP2
R/W
0
1
WDP1
R/W
0
0
WDP0
R/W
0
WDTCSR
 Bit 7 – WDIF: Watchdog Timeout Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by
writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
 Bit 6 – WDIE: Watchdog Timeout Interrupt Enable
When this bit is written to one, WDE is cleared, and the I-bit in the Status Register is set, the Watchdog Time-out
Interrupt is enabled. In this mode the corresponding interrupt is executed instead of a reset if a timeout in the Watchdog
Timer occurs.
If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is useful for keeping the
Watchdog Reset security while using the interrupt. After the WDIE bit is cleared, the next time-out will generate a reset.
To avoid the Watchdog Reset, WDIE must be set after each interrupt.
Table 8-4. Watchdog Timer Configuration
WDE
0
0
1
1
WDIE
0
1 ⁽¹⁾
0
1 ⁽¹⁾
Watchdog Timer State
Stopped
Running
Running
Running
Action on Time-out
None
Interrupt
Reset
Interrupt
Note: 1. In safety level 2, WDIE can not be set.
 Bit 4 – Res: Reserved
This bit is reserved and will always read zero.
 Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the
Watchdog Timer function is disabled.
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. See “Timed
Sequences for Changing the Configuration of the Watchdog Timer” on page 45.
In safety level 1, WDE is overridden by WDRF in MCUSR. See “MCUSR – MCU Status Register” on page 46 for
description of WDRF. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared
before disabling the Watchdog with the procedure described above. This feature ensures multiple resets during
conditions causing failure, and a safe start-up after the failure.
If the watchdog timer is not going to be used in the application, it is important to go through a watchdog disable procedure
in the initialization of the device. If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out
condition, the device will be reset, which in turn will lead to a new watchdog reset. To avoid this situation, the application
software should always clear the WDRF flag and the WDE control bit in the initialization routine.
ATtiny441/841 [DATASHEET] 47
8495H–AVR–05/2014