ATTINY441_14 Datasheet, PDF (194/366 Pages) ATMEL Corporation – 8-bit AVR Microcontroller with 4/8K Bytes In-System

19.8.3 UCSRnB – USART MSPIM Control and Status Register n B
Bit
(0x85)
Read/Write
Initial Value
7
6
5
4
3
2
1
0
RXCIE0
TXCIE0
UDRIE0
RXEN0
TXEN0
–
–
–
UCSR0B
R/W
R/W
R/W
R/W
R/W
R
R
R
0
0
0
0
0
0
0
0
Bit
(0x95)
Read/Write
Initial Value
7
6
5
4
3
2
1
0
RXCIE1
TXCIE1
UDRIE1
RXEN1
TXEN1
–
–
–
UCSR1B
R/W
R/W
R/W
R/W
R/W
R
R
R
0
0
0
0
0
0
0
0
 Bit 7 – RXCIEn: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXCn flag. A USART Receive Complete interrupt will be generated only if
the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXCn bit is set.
 Bit 6 – TXCIEn: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXCn flag. A USART Transmit Complete interrupt will be generated only if
the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit is set.
 Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDREn flag. A Data Register Empty interrupt will be generated only if the
UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit is set.
 Bit 4 – RXENn: Receiver Enable
Writing this bit to one enables the USART Receiver in MSPIM mode. When enabled, the receiver overrides normal port
operation for the RxDn pin.
Disabling the receiver will flush the receive buffer.
Enabling the receiver, only, and leaving the transmitter disabled has no meaning in MSPI mode since only master mode
is supported and it is the transmitter that controls the transfer clock.
 Bit 3 – TXENn: Transmitter Enable
Writing this bit to one enables the USART Transmitter. When enabled, the transmitter overrides normal port operation for
the TxDn pin.
Disabling the transmitter will not become effective until ongoing and pending transmissions are completed, i.e., when the
transmit shift register and transmit buffer register do not contain data to be transmitted. When disabled, the transmitter
will no longer override the TxDn pin.
 Bits 2:0 – Reserved Bits in MSPI mode
In MSPI mode these bits are reserved for future use. For compatibility with future devices, these bits must be written
zero.
ATtiny441/841 [DATASHEET] 194
8495H–AVR–05/2014