ATMEGA640V_0701 Datasheet, PDF (47/449 Pages) ATMEL Corporation – 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash

ATmega640/1280/1281/2560/2561
System Clock Prescaler
The ATmega640/1280/1281/2560/2561 has a system clock prescaler, and the system
clock can be divided by setting the “CLKPR – Clock Prescale Register” on page 48. This
feature can be used to decrease the system clock frequency and the power consump-
tion when the requirement for processing power is low. This can be used with all clock
source options, and it will affect the clock frequency of the CPU and all synchronous
peripherals. clk_I/O, clk_ADC, clk_CPU, and clk_FLASH are divided by a factor as shown in Table
23.
When switching between prescaler settings, the System Clock Prescaler ensures that
no glitches occurs in the clock system. It also ensures that no intermediate frequency is
higher than neither the clock frequency corresponding to the previous setting, nor the
clock frequency corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided
clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to
determine the state of the prescaler - even if it were readable, and the exact time it takes
to switch from one clock division to the other cannot be exactly predicted. From the time
the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new
clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is
the previous clock period, and T2 is the period corresponding to the new prescaler
setting.
To avoid unintentional changes of clock frequency, a special write procedure must be
followed to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits
in CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while writing a zero to
CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write pro-
cedure is not interrupted.
47
2549K–AVR–01/07