AT572D940HF_08 Datasheet, PDF (47/745 Pages) ATMEL Corporation – DIOPSIS 940HF ARM926EJ-S PLUS ONE GFLOPS DSP

AT572D940HF Preliminary
Since the protection domain remains unchanged on a interrupt, the Interrupt Service Routine is
called as a normal function call.
There are 8 prioritized interrupt lines. Line0 and line1 multiplex four lines each (named shared
lines), so that the number of interrupt lines is 14. Each interrupt line is associated to a 16 bit
interrupt vector register (MGCINTSVR) that must be set to a valid program address, correspond-
ing to the handler interrupt routine. An interrupt, on a previously enabled and not masked
interrupt line (via the MGCINTCTRL register), is registered into the PEND field of the MGCINT-
STAT interrupt status register.
Interrupts can be masked using the MGCINTMASK, a masked interrupt is always registered as
a pending interrupt, but it won't be served until it's masked.
When the program jumps to an Interrupt Service Routine the ISVR MGCSTAT bit will be set,
indicating that no more interrupts will be served until a return from interrupt instruction (RETI) is
executed. The user code return address is saved into the MGCINTRET register and it's automat-
ically restored into the MGCPC register when a RETI issue is executed.
In case of more than one pending interrupts, the line having higher priority will be served, in case
of equal priority the interrupt line with a lower number will be served.
The priority register MGCINTPRIO is a 24 bit register that allows to associate three priority bits
to each line.
Pending interrupts can be set and cleared by using MGCINTSETRESET; this feature can be
used to generate or clear interrupts by software over each line. Sleep and wake-up.
6.16.2
Sleep and Wakeup
mAgicV can go to sleep mode by writing the MGCCTRL register or by using the explicit FLOW
codes. The processor will be waken up by one of the interrupts, or by four EOT (End of Transfer)
events coming from the DMA. The events that can wake mAgicV up from a sleep state are
selected using the MGCWAKECTRL control register.
6.16.3
Exceptions
mAgicV exceptions are divided into fatal and non fatal exceptions. Non masked fatal exceptions
cause the processor to stop immediately and to enter into debug mode. Other exceptions can be
handled in run mode by the exception interrupt routine number 6. Exception register MGCEX-
CEPTION collects exceptions.
6.17 Profiling Registers
The user is able to evaluate the performance of the system through two mAgicV 32 bit counter
registers.
The MGCSTEP register is used to collect information on the cycles spent in run mode. It
includes the cycles of pipeline stall due to program cache miss or sleep mode. This counter can
be accessed by mAgicV and by an external AHB master controller.
It is possible to start and to stop the MGCSTEP counter register by accessing respectively
TICKON and TICKOFF MGCCTRL control bits . An interrupt handler can be installed on INT #7
line, signalling the overflow of this counter. The overflow is registered in the MGCSTAT register
and it’s cleared by write operations on the MGCSTEP register.
The PMUMISSCNT register is used to collect information about the number of programs mis-
done. This register can be accessed only by an external AHB master controller.
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