|
AT572D940HF_08 Datasheet, PDF (1/745 Pages) ATMEL Corporation – DIOPSIS 940HF ARM926EJ-S PLUS ONE GFLOPS DSP | |||
|
Features
⢠DIOPSIS® Dual Core System Integrating an ARM926EJ-S⢠ARM® Thumb® Processor
Core and a MagicV of VLIW Magic DSP⢠is optimized for Audio, Communication and
Beam-forming Applications
⢠High Performance MagicV VLIW DSP
â 1 GFLOPS - 1.6 Gops at 100 MHz
â AHB Master Port, integrated DMA Engine and AHB Slave Port
â Up to 10 Arithmetic Operations per Cycle (4 Multiply, 2 Add/Subtract, 1 Add, 1
Subtract 40-bit Floating Point and 32-bit Integer) allowing Single Cycle FFT
Butterfly
â Native Support for Complex Arithmetic and Vectorial SIMD Operations: One
Complex Multiply with Dual Add/Sub per Clock Cycle or Two Multiply and Two
Add/sub or Simple Scalar Operations
â 32-bit Integer and IEEE® 40-bit Extended Precision Floating Point Numeric Format
â 16-port Data Register File: 256 Registers organized in Two 128-register Banks
â 5-issue predicated VLIW Architecture with Orthogonal ISA, Code Compression
and Hardware Support for Code Efficient Software Pipeline Loops
â 6 Accesses per Cycle Data Memory System (4 Accesses per Cycle for VLIW
Operations + 2 Accesses per Cycle for DMA Transfers) supported by Flexible
Addressing Capability
â 2 Independent Address Generation Units Operating on a 64-register Address
Register File Supporting Complex or Micro-Vectorial Accesses and DSP features:
Programmable Stride and Circular Buffers
â 1.7 Mbits of On-chip SRAM:
â 16 K x 40-bit Data Memory Locations (6 Memory Accesses per Cycle)
â 8 K x 128-bit Dual Port Program Memory Location, Equivalent to ~50K DSP
Assembler Instructions (typical) thanks to Code Compression and SW Pipelining
â DMA Access to the External Program and Data Memory
â Three Main Operating Modes: Run, Debug and Sleep
â User Mode and Privileged Interrupt Service Mode
â Efficient Optimizing Assembler and C-Oriented Architecture: allows Easy
Exploitation of the available Hardware Parallelism
â ARM926EJ-S ARM Thumb Processor
â DSP Instruction Extensions
â ARM Jazelle® Technology for Java® Acceleration
â 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer
â 220MIPS at 200MHz
â Memory Management Unit
â EmbeddedICE⢠In-circuit Emulation, Debug Communication Channel Support
⢠Additional Embedded Memories
â 32-KByte of internal ROM, two-cycle access at maximum bus speed
â 48-KByte of internal SRAM, single-cycle access at maximum processor or bus
speed
⢠External Bus Interface (EBI)
â Supports SDRAM, Static Memory, SmartMedia⢠and NAND Flash, CompactFlashâ¢
⢠USB
â USB 2.0 Full Speed (12 Mbits per second) Host Double Port
â Dual On-chip Transceivers
â Integrated FIFOs and Dedicated DMA Channels
DIOPSIS 940HF
ARM926EJ-S PLUS
ONE GFLOPS DSP
AT572D940HF
Preliminary
7010AâDSPâ07/08
|
▷ |