AT90PWM3 Datasheet, PDF (46/365 Pages) ATMEL Corporation – 8-bit Microcontroller with 8K Bytes In-System Programmable Flash

Power-on Reset
External Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-
tion level is defined in Table 14. The POR is activated whenever V_CC is below the
detection level. The POR circuit can be used to trigger the start-up Reset, as well as to
detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reach-
ing the Power-on Reset threshold voltage invokes the delay counter, which determines
how long the device is kept in RESET after V_CC rise. The RESET signal is activated
again, without any delay, when V_CC decreases below the detection level.
Figure 18. MCU Start-up, RESET Tied to V_CC
V_CC
V_POT
RESET
V_RST
TIME-OUT
t_TOUT
INTERNAL
RESET
Figure 19. MCU Start-up, RESET Extended Externally
V_CC
RESET
V_POT
V_RST
TIME-OUT
t_TOUT
INTERNAL
RESET
An External Reset is generated by a low level on the RESET pin. Reset pulses longer
than the minimum pulse width (see Table 14) will generate a reset, even if the clock is
not running. Shorter pulses are not guaranteed to generate a reset. When the applied
signal reaches the Reset Threshold Voltage – V_RST – on its positive edge, the delay
counter starts the MCU after the Time-out period – t_TOUT – has expired.
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