AT90PWM3 Datasheet, PDF (171/365 Pages) ATMEL Corporation – 8-bit Microcontroller with 8K Bytes In-System Programmable Flash

AT90PWM2/3
PSC 0 Configuration Register
– PCNF0
Bit
Read/Write
Initial Value
7
PFIFTY0
R/W
0
6
PALOCK0
R/W
0
5
4
3
PLOCK0 PMODE01 PMODE00
R/W
R/W
R/W
0
0
0
2
POP0
R/W
0
1
PCLKSEL0
R/W
0
0
-
R/W
0
PCNF0
PSC 1 Configuration Register
– PCNF1
Bit
Read/Write
Initial Value
7
PFIFTY1
R/W
0
6
PALOCK1
R/W
0
5
4
3
PLOCK1 PMODE11 PMODE10
R/W
R/W
R/W
0
0
0
2
POP1
R/W
0
1
PCLKSEL1
R/W
0
0
-
R/W
0
PCNF0
PSC 2 Configuration Register
– PCNF2
Bit
Read/Write
Initial Value
7
PFIFTY2
R/W
0
6
PALOCK2
R/W
0
5
4
3
PLOCK2 PMODE21 PMODE20
R/W
R/W
R/W
0
0
0
2
POP2
R/W
0
1
PCLKSEL2
R/W
0
0
POME2
R/W
0
PCNF0
The PSC n Configuration Register is used to configure the running mode of the PSC.
• Bit 7 - PFIFTYn: PSC n Fifty
Writing this bit to one, set the PSC in a fifty percent mode where only OCRnRBH/L and
OCRnSBH/L are used. They are duplicated in OCRnRAH/L and OCRnSAH/L during the
update of OCRnRBH/L. This feature is useful to perform fifty percent waveforms.
• Bit 6 - PALOCKn: PSC n Autolock
When this bit is set, the Output Compare Registers RA, SA and SB can be written with-
out disturbing the PSC cycles. The update of the PSC internal registers will be done at
the end of the PSC cycle if the Output Compare Register RB has been the last written.
When set, this bit prevails over LOCK (bit 5)
• Bit 5 – PLOCKn: PSC n Lock
When this bit is set, the Output Compare Registers RA, RB, SA and SB can be written
without disturbing the PSC cycles. The update of the PSC internal registers will be done
if the LOCK bit is released to zero.
• Bit 4:3 – PMODEn1: 0: PSC n Mode
Select the mode of PSC.
Table 64. PSC n Mode Selection
PMODEn1 PMODEn0 Description
0
0
One Ramp Mode
0
1
Two Ramp Mode
1
0
Four Ramp Mode
1
1
Center Aligned Mode
• Bit 2 – POPn: PSC n Output Polarity
If this bit is cleared, the PSC outputs are active Low.
If this bit is set, the PSC outputs are active High.
4317A-3–AVR–02/05
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