AT91SAM9G20_14 Datasheet, PDF (454/832 Pages) ATMEL Corporation – Incorporates the ARM926EJ-S ARM Thumb Processor

31.10.7 TWI Interrupt Enable Register
Name:
TWI_IER
Access:
Write-only
Reset Value: 0x00000000
31
30
29
28
27
–
–
–
–
–
23
22
21
20
19
–
–
–
–
–
15
TXBUFE
14
RXBUFF
13
ENDTX
12
ENDRX
11
EOSACC
7
6
5
4
3
–
OVRE
GACC
SVACC
–
• TXCOMP: Transmission Completed Interrupt Enable
• RXRDY: Receive Holding Register Ready Interrupt Enable
• TXRDY: Transmit Holding Register Ready Interrupt Enable
• SVACC: Slave Access Interrupt Enable
• GACC: General Call Access Interrupt Enable
• OVRE: Overrun Error Interrupt Enable
• NACK: Not Acknowledge Interrupt Enable
• ARBLST: Arbitration Lost Interrupt Enable
• SCL_WS: Clock Wait State Interrupt Enable
• EOSACC: End Of Slave Access Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable
0 = No effect.
1 = Enables the corresponding interrupt.
26
–
18
–
10
SCL_WS
2
TXRDY
25
–
17
–
9
ARBLST
1
RXRDY
24
–
16
–
8
NACK
0
TXCOMP
454 AT91SAM9G20
6384E–ATARM–05-Feb-10