AT91SAM9G20_14 Datasheet, PDF (271/832 Pages) ATMEL Corporation – Incorporates the ARM926EJ-S ARM Thumb Processor

AT91SAM9G20
24.4 Peripheral DMA Controller (PDC) User Interface
Table 24-1. Register Mapping
Offset
0x100
Register
Receive Pointer Register
Name
PERIPH⁽¹⁾_RPR
Access
Read-write
Reset
0
0x104
Receive Counter Register
PERIPH_RCR
Read-write
0
0x108
Transmit Pointer Register
PERIPH_TPR
Read-write
0
0x10C
Transmit Counter Register
PERIPH_TCR
Read-write
0
0x110
Receive Next Pointer Register
PERIPH_RNPR
Read-write
0
0x114
Receive Next Counter Register
PERIPH_RNCR
Read-write
0
0x118
Transmit Next Pointer Register
PERIPH_TNPR
Read-write
0
0x11C
Transmit Next Counter Register
PERIPH_TNCR
Read-write
0
0x120
Transfer Control Register
PERIPH_PTCR
Write-only
0
0x124
Transfer Status Register
PERIPH_PTSR
Read-only
0
Note: 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user
according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI, etc.)
6384E–ATARM–05-Feb-10
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