TS80C51RA2_02 Datasheet, PDF (45/83 Pages) ATMEL Corporation – High Performance 8-bit Microcontroller

Hardware Watchdog
Timer
Using the WDT
4188A–8051–10/02
TS8xC51Rx2
The WDT is intended as a recovery method in situations where the CPU may be sub-
jected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer
ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable
the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location
0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator
is running and there is no way to disable the WDT except through reset (either hardware
reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH
pulse at the RST-pin.
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR
location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH
and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it
reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will
increment every machine cycle while the oscillator is running. This means the user must
reset the WDT at least every 16383 machine cycle. To reset the WDT the user must
write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter
cannot be read or written. When WDT overflows, it will generate an output RESET pulse
at the RST-pin. The RESET pulse duration is 96 x T_OSC , where T_OSC = 1/F_OSC . To
make the best use of the WDT, it should be serviced in those sections of code that will
periodically be executed within the time required to prevent a WDT reset.
To have a more powerful WDT, a 2⁷ counter has been added to extend the Time-out
capability, ranking from 16ms to 2s @ F_OSC = 12MHz. To manage this feature, refer to
WDTPRG register description, Table 26 (SFR0A7h).
Table 25. WDTRST Register
WDTRST Address (0A6h)
7
6
5
4
3
2
1
Reset value
X
X
X
X
X
X
X
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in
sequence.
Table 26. WDTPRG Register
WDTPRG Address (0A7h)
7
6
5
4
3
2
1
0
T4
T3
T2
T1
T0
S2
S1
S0
Bit
Bit
Number Mnemonic Description
7
T4
6
T3
5
T2
Reserved
Do not try to set or clear this bit.
4
T1
3
T0
2
S2
WDT Time-out select bit 2
1
S1
WDT Time-out select bit 1
0
S0
WDT Time-out select bit 0
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