AT32UC3A0512 Datasheet, PDF (45/52 Pages) ATMEL Corporation – AVR32 32-Bit Microcontroller

13. Ordering Information
Device
AT32UC3A0512
AT32UC3A1512
AT32UC3A0256
AT32UC3A1256
AT32UC3A0128
AT32UC3A1128
14. Errata
14.1 Rev. E
Ordering Code
AT32UC3A0512-ALUT
AT32UC3A1512-AUT
AT32UC3A0256-ALUT
AT32UC3A1256-AUT
AT32UC3A0128-ALUT
AT32UC3A1128-AUT
Package
144 lead LQFP
100 lead TQFP
144 lead LQFP
100 lead TQFP
100 lead TQFP
100 lead TQFP
Conditioning
Tray
Tray
Tray
Tray
Tray
Tray
Temperature Operating
Range
Industrial (-40°C to 85°C)
Industrial (-40°C to 85°C)
Industrial (-40°C to 85°C)
Industrial (-40°C to 85°C)
Industrial (-40°C to 85°C)
Industrial (-40°C to 85°C)
1. SPI FDIV option does not work
Selecting clock signal using FDIV = 1 does not work as specified.
Fix/Workaround
Do not set FDIV = 1.
2. PWM counter restarts at 0x0001
The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first
PWM period has one more clock cycle.
Fix/Workaround
- The first period is 0x0000, 0x0001, ..., period
- Consecutive periods are 0x0001, 0x0002, ..., period
3. PWM channel interrupt enabling triggers an interrupt
When enabling a PWM channel that is configured with center aligned period (CALG=1), an
interrupt is signalled.
Fix/Workaround
When using center aligned mode, enable the channel and read the status before channel
interrupt is enabled.
4. PWM update period to a 0 value does not work
It is impossible to update a period equal to 0 by the using the PWM update register
(PWM_CUPD).
Fix/Workaround
Do not update the PWM_CUPD register with a value equal to 0.
5. PWM channel status may be wrong if disabled before a period has elapsed
Before a PWM period has elapsed, the read channel status may be wrong. The CHIDx-bit
for a PWM channel in the PWM Enable Register will read '1' for one full PWM period even if
the channel was disabled before the period elapsed. It will then read '0' as expected.
Fix/Workaround
45
32058AS–AVR32–03/07