AT32UC3A0512 Datasheet, PDF (20/52 Pages) ATMEL Corporation – AVR32 32-Bit Microcontroller

Table 9-1. Peripheral Address Mapping (Continued)
Address
Peripheral Name
0xFFFF1C00
0xFFFF2000
0xFFFF2400
0xFFFF2800
0xFFFF2C00
0xFFFF3000
0xFFFF3400
0xFFFF3800
0xFFFF3C00
USART2
USART3
SPI0
SPI1
TWI
PWM
SSC
TC
ADC
Universal Synchronous Asynchronous Receiver
Transmitter - USART2
Universal Synchronous Asynchronous Receiver
Transmitter - USART3
Serial Peripheral Interface - SPI0
Serial Peripheral Interface - SPI1
Two Wire Interface - TWI
Pulse Width Modulation Controller - PWM
Synchronous Serial Controller - SSC
Timer/Counter - TC
Analog To Digital Converter - ADC
Bus
PBA
PBA
PBA
PBA
PBA
PBA
PBA
PBA
PBA
9.2 Interrupt Request Signal Map
The various modules may output Interrupt request signals. These signals are routed to the Inter-
rupt Controller (INTC), described in a later chapter. The Interrupt Controller supports up to 64
groups of interrupt requests. Each group can have up to 32 interrupt request signals. All interrupt
signals in the same group share the same autovector address and priority level. Refer to the
documentation for the individual submodules for a description of the semantic of the different
interrupt requests.
The interrupt request signals are connected to the INTC as follows.
Table 9-2.
Group
0
Interrupt Request Signal Map
Line
Module
0
Peripheral DMA Controller
Signal
PDCA 16
20
32058AS–AVR32–03/07