AT91SAM9260_1 Datasheet, PDF (44/798 Pages) ATMEL Corporation – AT91 ARM Thumb Microcontrollers

10.6
Memory Management Unit (MMU)
The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide vir-
tual memory features required by operating systems like Symbian OS^®, Windows CE, and
Linux. These virtual memory features are memory access permission controls and virtual to
physical address translations.
The Virtual Address generated by the CPU core is converted to a Modified Virtual Address
(MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13. The
MMU translates modified virtual addresses to physical addresses by using a single, two-level
page table set stored in physical memory. Each entry in the set contains the access permissions
and the physical address that correspond to the virtual address.
The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These
entries contain a pointer to either a 1 MB section of physical memory along with attribute infor-
mation (access permissions, domain, etc.) or an entry in the second level translation tables;
coarse table and fine table.
The second level translation tables contain two subtables, coarse table and fine table. An entry
in the coarse table contains a pointer to both large pages and small pages along with access
permissions. An entry in the fine table contains a pointer to large, small and tiny pages.
Table 10-6 shows the different attributes of each page in the physical memory.
Table 10-6. Mapping Details
Mapping Name
Mapping Size
Section
1M byte
Large Page
64K bytes
Small Page
4K bytes
Tiny Page
1K byte
Access Permission By
Section
4 separated subpages
4 separated subpages
Tiny Page
Subpage Size
-
16K bytes
1K byte
-
The MMU consists of:
• Access control logic
• Translation Look-aside Buffer (TLB)
• Translation table walk hardware
10.6.1
Access Control Logic
The access control logic controls access information for every entry in the translation table. The
access control logic checks two pieces of access information: domain and access permissions.
The domain is the primary access control mechanism for a memory region; there are 16 of them.
It defines the conditions necessary for an access to proceed. The domain determines whether
the access permissions are used to qualify the access or whether they should be ignored.
The second access control mechanism is access permissions that are defined for sections and
for large, small and tiny pages. Sections and tiny pages have a single set of access permissions
whereas large and small pages can be associated with 4 sets of access permissions, one for
each subpage (quarter of a page).
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