AT91SAM9260_1 Datasheet, PDF (183/798 Pages) ATMEL Corporation – AT91 ARM Thumb Microcontrollers

AT91SAM9260
20.10.2
TDF Optimization Enabled (TDF_MODE = 1)
When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the
SMC takes advantage of the setup period of the next access to optimize the number of wait
states cycle to insert.
Figure 20-22 shows a read access controlled by NRD, followed by a write access controlled by
NWE, on Chip Select 0. Chip Select 0 has been programmed with:
NRD_HOLD = 4; READ_MODE = 1 (NRD controlled)
NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled)
TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled).
Figure 20-22. TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins
MCK
A[25:2]
NRD
NWE
NRD_HOLD= 4
NCS0
D[31:0]
NWE_SETUP= 3
TDF_CYCLES = 6
read access on NCS0 (NRD controlled)
Read to Write
Wait State
write access on NCS0 (NWE controlled)
20.10.3
TDF Optimization Disabled (TDF_MODE = 0)
When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that
the data float period is ended when the second access begins. If the hold period of the read1
controlling signal overlaps the data float period, no additional tdf wait states will be inserted.
Figure 20-23, Figure 20-24 and Figure 20-25 illustrate the cases:
• read access followed by a read access on another chip select,
• read access followed by a write access on another chip select,
• read access followed by a write access on the same chip select,
with no TDF optimization.
6221I–ATARM–17-Jul-09
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