AT17F32_14 Datasheet, PDF (4/14 Pages) ATMEL Corporation – 3.3V Output Capability

5. Pin Description
5.1 DATA⁽¹⁾
Table 5-1. Pin Description
Name
I/O
DATA
I/O
CLK
I
PAGE_EN
I
PAGESEL0
I
PAGESEL1
I
RESET/OE
I
CE
I
GND
–
CEO
O
A2
I
READY
O
SER_EN
I
V_CC
–
AT17F32
44
PLCC
2
5
1
20
25
19
21
24
27
29
41
44
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
5.2 CLK⁽¹⁾
Clock input. Used to increment the internal address and bit counter for reading and
programming.
5.3 PAGE_EN⁽²⁾
Input used to enable page download mode. When PAGE_EN is high the configuration download
address space is partitioned into 4 equal pages. This gives users the ability to easily store and
retrieve multiple configuration bitstreams from a single configuration device. This input works in
conjunction with the PAGESEL inputs. PAGE_EN must be remain Low if paging is not desired.
When SER_EN is Low (ISP mode) this pin has no effect.
Notes: 1. This pin has an internal 20 KΩ pull-up resistor.
2. This pin has an internal 30 KΩ pull-down resistor.
4 AT17F32
3393C–CNFG–6/05