AT91SAM7S64-AI Datasheet, PDF (392/482 Pages) ATMEL Corporation – AT91 ARM THUMB BASED MICROCONTROLLERS

PWM Channel Period Register
Register Name: PWM_CPRDx
Access Type: Read/Write
31
30
29
28
27
26
25
24
CPRD
23
22
21
20
19
18
17
16
CPRD
15
14
13
12
11
10
9
8
CPRD
7
6
5
4
3
2
1
0
CPRD
Only the first 16 bits (internal channel counter size) are significative.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula will be:
(_---X_-----×_-M----C_--C--P_--K--R_----D_-----)_-
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
(_---C_----R_----P_----D_------×_-----D_-----I_--V_----A_----)_{- or} (_---C_----R_----P_----D_------×_-----D_-----I_--V_----A_----B_----)_-
MCK
MCK
If the waveform is center-aligned, then the output waveform period depends on the counter source clockand can be
calculated:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula will be:
(_---2_-----×_-----X_-----×_----C_-----P_----R_----D_-----)
MCK
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
(_---2_-----×_-----C_----P_----R_----D_------×_-----D_----I_---V_----A_----) _or (_---2_-----×_-----C_----P_----R_----D_------×_-----D_----I_---V_----B_----)
MCK
MCK
392 AT91SAM7S64 Preliminary
6070A–ATARM–28-Oct-04