AT91RM9200_14 Datasheet, PDF (374/701 Pages) ATMEL Corporation – 200 MIPS at 180 MHz, Memory Management Unit

28.4 Product Dependencies
28.4.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
The programmer must first program the PIO controllers to assign the SPI pins to their peripheral
functions.
28.4.2
Power Management
The SPI may be clocked through the Power Management Controller (PMC), thus the program-
mer must first have to configure the PMC to enable the SPI clock.
28.4.3 Interrupt
The SPI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).
Handling the SPI interrupt requires programming the AIC before configuring the SPI.
28.5 Functional Description
28.5.1
Master Mode Operations
When configured in Master Mode, the Serial Peripheral Interface controls data transfers to and
from the slave(s) connected to the SPI bus. The SPI drives the chip select(s) to the slave(s) and
the serial clock (SPCK). After enabling the SPI, a data transfer begins when the core writes to
the SPI_TDR (Transmit Data Register).
Transmit and Receive buffers maintain the data flow at a constant rate with a reduced require-
ment for high-priority interrupt servicing. When new data is available in the SPI_TDR, the SPI
continues to transfer data. If the SPI_RDR (Receive Data Register) has not been read before
new data is received, the Overrun Error (OVRES) flag is set.
Note: As long as this flag is set, no data is loaded in the SPI_RDR. The user has to read the status reg-
ister to clear it.
The programmable delay between the activation of the chip select and the start of the data
transfer (DLYBS), as well as the delay between each data transfer (DLYBCT), can be pro-
grammed for each of the four external chip selects. All data transfer characteristics, including the
two timing values, are programmed in registers SPI_CSR0 to SPI_CSR3 (Chip Select
Registers).
In Master Mode, the peripheral selection can be defined in two different ways:
• Fixed Peripheral Select: SPI exchanges data with only one peripheral
• Variable Peripheral Select: Data can be exchanged with more than one peripheral
Figure 28-7 and Figure 28-8 show the operation of the SPI in Master Mode. For details concern-
ing the flag and control bits in these diagrams, see the “Serial Peripheral Interface (SPI) User
Interface” on page 382 and the subsequent register descriptions.
28.5.1.1
Fixed Peripheral Select
This mode is used for transferring memory blocks without the extra overhead in the transmit data
register to determine the peripheral.
Fixed Peripheral Select is activated by setting bit PS to zero in SPI_MR (Mode Register). The
peripheral is defined by the PCS field in SPI_MR.
This option is only available when the SPI is programmed in Master Mode.
374 AT91RM9200
1768I–ATARM–09-Jul-09